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Re: Better DES challenge update

daemon@ATHENA.MIT.EDU (Andreas Bogk)
Tue Jul 1 16:48:12 1997

To: die@die.com
Cc: eli@gs160.sp.cs.cmu.edu (Eli Brandt), cryptography@c2.net,
        crisp@netcom.com (Richard Crisp)
From: Andreas Bogk <andreas@artcom.de>
Date: 30 Jun 1997 18:36:04 +0200
In-Reply-To: Dave Emery's message of Sun, 29 Jun 1997 20:32:58 -0400 (EDT)

>>>>> "Dave" == Dave Emery <die@pig.die.com> writes:

    Dave> 	As I see such an architecture, the ASIC would either
    Dave> contain a second slow DES path (more or less similar to a
    Dave> current DES chip and not pipelined like the main engine) or
    Dave> logic to insert out of order keys into the main pipelined
    Dave> engine.  This would allow the chip to buffer in a FIFO and
    Dave> asynchronously test hits on possible keys to any reasonable
    Dave> desired depth without going off chip. This architecture

Of course, just building sixteen un-pipelined engines would require
about the same number of gates. It could even be more efficient (in
terms of cost vs. speed) not to test hits before round 16.

Andreas

P.S.: It's about time to announce this in public. The Chaos Computer
Club, Berlin, Germany, raises funds to build a DES cracker
hardware. Of course we won't be doing this unless one or two
substantial donations by major companies arrive, but we're faithful.

-- 
Get rid of C++ and yourself a Dylan compiler at legend.gwydion.cs.cmu.edu!




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