[1164] in cryptography@c2.net mail archive
Re: Better DES challenge update
daemon@ATHENA.MIT.EDU (Andreas Bogk)
Thu Jul 3 16:58:43 1997
To: Steven Bellovin <smb@research.att.com>
Cc: die@die.com, eli@gs160.sp.cs.cmu.edu, cryptography@c2.net,
crisp@netcom.com
From: Andreas Bogk <andreas@artcom.de>
Date: 03 Jul 1997 21:06:37 +0200
In-Reply-To: Steven Bellovin's message of Wed, 02 Jul 1997 20:21:15 -0400
>>>>> "Steven" == Steven Bellovin <smb@research.att.com> writes:
Steven> Let me point to two papers:
Steven> ftp://ftp.research.att.com/dist/smb/recog.ps
This is very interesting, but unfortunately there's not enough RAM on
a typical FPGA to implement digraph statistics. On the other hand,
there's plenty of RAM for single character statistics.
The Wiener design hardly fits on todays FPGAs, the S-boxes already eat
up 80% of the logic functions of an Altera 10K100. It's hard to tell
wheter the rest of the logic fits as well.
Of course, implementing a single stage DES would leave enogh room and
16 clock ticks for more complex statistics.
On an ASIC, this is a very sensible extension in any case.
Andreas
--
Get rid of C++ and yourself a Dylan compiler at legend.gwydion.cs.cmu.edu!
