[4083] in cryptography@c2.net mail archive
Pentium III serial number mechanism
daemon@ATHENA.MIT.EDU (Markus Kuhn)
Thu Jan 28 12:49:13 1999
To: cryptography@c2.net, coderpunks@toad.com
In-reply-to: Your message of "Tue, 26 Jan 1999 18:10:00 GMT."
<E105CwK-0007Qi-00@heaton.cl.cam.ac.uk>
Date: Thu, 28 Jan 1999 17:27:18 +0000
From: Markus Kuhn <Markus.Kuhn@cl.cam.ac.uk>
Keith Lofstrom <keithl@chip.klic.rain.com> has sent me a very good
argument for why the serial number is probably not at all located on the
die (forwarded below with permission). This goes also very well with
earlier rumours that I have heard that the now officially announced
Pentium III features are actually implemented in the chip set and not in
the very critical CPU die itself. There are certainly manufacturers such
as Dallas Semiconductor who can do laser programming of serial numbers for
security processors directly onto the CPU die, but these are low-cost
microcontrollers and not Pentium-grade devices where everything is much
more difficult.
Makes sense to me. Here is Keith's argument (forwarded with permission):
------------------------------------------------------------------------
From: Keith Lofstrom <keithl@chip.klic.rain.com>
Subject: Pentium III mechanism
Date: Thu, 28 Jan 1999 09:00:31 -0800 (PST)
Regards the Pentium III programming mechanism:
I'm not on the cryptography mailing list, just reading mail-archive.com.
Forward this if you deem it worthwhile. You folks run a very polite
list given the volatility of the topic. Kudos.
---
The Pentium III may very well follow the techniques used on the
Pentium II and the Xeon. The Xeon uses a separate, serially
accessed EEPROM chip in the cartridge. There are some good
reasons for this:
1) Designing "extra" technology into the Pentium III process will
delay its introduction. A week delay in the introduction of a
new processor costs Intel about a billion dollars. It shortens
the very narrow window of "cream skimming" until prices are
eroded by competition. Moore's law can be restated as "1% performance
per week." And at Intel, Moore's law is not just a good idea...
2) Yield and reliability and fab time of the extra steps.
3) Tester time for Pentium-speed devices is very expensive - perhaps
30 cents per second. It is cheaper to put an extra flash chip in the
cartridge, costing perhaps 10 cents, than spend another half of a
second cooking fuses or NVRAM cells on the CPU tester, which take
a long time (milliseconds!) to heat or move charge. Best to do this
on an ancient ( > 2 year old ) chip tester separately from the CPU.
4) Same thing applies to lasers (moving mirrors - horrors!) with
the additional difficulty that laser systems fail or go out of
mechanical alignment, reducing throughput on the $1000/hr tester.
And laser targets need a lot of die real estate.
5) Treating the CPU wafer to a separate pass through a "programming
tester" might make sense - but this costs you in "scrub yield".
Every time you drop a probe on a pad, you have to contact it strongly
enough to scrub through any surface oxides that have formed. You tear
it up a bit, reducing its reliability later after it is permanently
bonded. Separate pads might make sense, but then you are back to the
real estate problem - a pad costs about half a penny on a Pentium-class
wafer.
There are tradeoffs, of course, and the cost and yield of a separate
chip in the cartridge may make the above costs relatively palatable.
Certainly when the Pentium die get complicated enough, lasers or fuses
for redundancy may make economic sense. But on a mature Pentium line
( > 3 months in production ) the yields become very good, while the
test time gets longer - minimizing expensive test time is a strong
driving force.
Economica and past history strongly points to a separate chip in the
cartridge. I hope those clever folks at Intel have something new
that proves me wrong.
Keith
--
Keith Lofstrom keithl@klic.rain.com Voice (503)-520-1993
KLIC --- Keith Lofstrom Integrated Circuits --- "Your Ideas in Silicon"
Design Contracting in Bipolar and CMOS - Analog, Digital, and Power ICs
