[98022] in cryptography@c2.net mail archive
=?UTF-8?B?QU1EcyBuZXcgaW5zdHJ1Y3Rpb25zIGZvciBwYXJhbGxlbGlzbSBhbmQ=?=
daemon@ATHENA.MIT.EDU (=?UTF-8?B?Sm9hY2hpbSBTdHLDtm1iZXJn)
Tue Aug 14 15:04:46 2007
Date: Tue, 14 Aug 2007 15:58:09 +0200
From: =?UTF-8?B?Sm9hY2hpbSBTdHLDtm1iZXJnc29u?= <Joachim@Strombergson.com>
To: cryptography@metzdowd.com
Aloha!
I just saw om EE Times that AMD will start to extend their x86 CPUs with
instructions to support/help developers take advantage of the increasing
(potential) parallelism in their processors. First out are two
instructions that allows the developer to get info about instruction
completion as well as cache misses.
Considering the article by . about analysis of protection mechanism
against cache based timing attacks for AES [1] one could assume that
these instructions should be useful for writing side-channel resistant
implementations
But, do you think that the opppsite is also possible, that these
instructions might be a possible source for information leackage and
vector for side-channel attacks, at least local, inter process attacks?
I get a weird goodie-badie feeling when reading about these instructions...
[1] Johannes Blömer and Volker Krummel. Analysis of countermeasures
against access driven cache attacks on AES
http://eprint.iacr.org/2007/282.pdf
--
Med vänlig hälsning, Yours
Joachim Strömbergson - Alltid i harmonisk svängning.
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