[148695] in cryptography@c2.net mail archive
Re: [Cryptography] [IP] 'We cannot trust' Intel and Via's
daemon@ATHENA.MIT.EDU (dj@deadhat.com)
Wed Dec 25 14:47:56 2013
X-Original-To: cryptography@metzdowd.com
In-Reply-To: <CAOLP8p4mFRn5B+yGv7QMinDoJRdGNVC1c2GR_-9Wy=77O36igg@mail.gmail.com>
Date: Wed, 25 Dec 2013 11:27:42 -0000
From: dj@deadhat.com
To: "Bill Cox" <waywardgeek@gmail.com>
Cc: "cryptography@metzdowd.com" <cryptography@metzdowd.com>
Errors-To: cryptography-bounces+crypto.discuss=bloom-picayune.mit.edu@metzdowd.com
> It's not publically documented, but I hear TSMC added extra transistors to
> some Xilinx FPGAs, and the last I heard, no one had figured out what they
> were for.
>
>
> On Tue, Dec 24, 2013 at 2:43 AM, ianG <iang@iang.org> wrote:
>
It would be normal to add characterization circuits to chips to measure
the properties of the silicon during and after manufacture. But if you
were doing your own layout, leaving space for these would be part of the
design rules.
Is there anything substantive to suggest it was something else?
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