[148698] in cryptography@c2.net mail archive
Re: [Cryptography] [IP] 'We cannot trust' Intel and Via's
daemon@ATHENA.MIT.EDU (Bill Cox)
Wed Dec 25 14:50:18 2013
X-Original-To: cryptography@metzdowd.com
Date: Wed, 25 Dec 2013 09:18:42 -0500
From: Bill Cox <waywardgeek@gmail.com>
To: dj@deadhat.com
In-Reply-To: <d5aee0cd6bdca61a6d2cbc4d585dfeec.squirrel@www.deadhat.com>
Cc: "cryptography@metzdowd.com" <cryptography@metzdowd.com>
Errors-To: cryptography-bounces+crypto.discuss=bloom-picayune.mit.edu@metzdowd.com
On 12/25/2013 6:27 AM, dj@deadhat.com wrote:
> It would be normal to add characterization circuits to chips to
> measure the properties of the silicon during and after manufacture.
> But if you were doing your own layout, leaving space for these would
> be part of the design rules. Is there anything substantive to suggest
> it was something else?
I heard this second hand, but the guy at the time was pretty freaked
out. I never heard what became of this story. Characterization
transistors are normally added in small gaps between die, not on the die
itself. Xilinx does a good job of using all the available area for
circuitry, even putting transistors in the corners where almost every
other die you'll see has nothing but wasted space, and some 45-degree
turns for IO power busing. The extra transistors were added in some of
the few remaining spaces that Xilinx didn't fill. The fact that I never
heard about this again probably means it either was not malicious or our
guys decided not to make it public for some reason.
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